There is a persistent goal in the semiconductor industry of making smaller elements in an integrated circuit structure so that more elements can be located on a single integrated circuit chip, and so that the elements have lower power requirement, lower capacitance, and higher operating speed. A widely used circuit element is a MOS transistor, in which a gate of polycrystalline silicon is located above the semiconductive substrate and source/drain regions are located in the substrate on either side of the gate. Gate arrays and other arrangements frequently employ adjacent MOS transistors which may share source/drain regions. FIGS. 1.1a through 1.3a and 1.1b through 1.3b show successive steps in the formation of a prior art structure having two adjacent MOS transistors sharing a central source/drain region. FIGS. 1.1a through 1.3a show top views of the structure and FIGS. 1.1b through 1.3b show side cross sectional views taken along line A--A. The same elements are indicated by the same reference numerals in successive figures.
As shown in FIGS. 1.1a and 1.1b two gates 12a and 12b extend across an exposed portion of substrate 10, which is surrounded by field oxide region 11. FIGS. 1.2a and 1.2b show insulating (typically silicon dioxide) side wall spacer regions 13a and 13b. These spacers are formed by well known processes. Typically this step is followed by formation of an insulation layer 14 such as silicon dioxide, which is patterned to form vias such as 14a, 14b, and 14c which expose substrate 10. Into these exposed substrate regions are implanted source/drain regions 15a, 15b, and 15c, which are shown in FIG. 1.3b as n+regions, but can of course be p-type regions if desired. A conductive material (not shown) is applied to the surface of the wafer and patterned to form contacts.
The above process requires separate masking steps, first for forming the gates and source/drain regions and second for opening the vias for contacting the conductive contacts. The two masks are not self aligned. Therefore, space must be allocated in the layout of the elements within the chip to allow for misalignment of these two masks. FIG. 1.3b shows contact openings 14a, 14b, and 14c misaligned with respect to gates 12a and 12b. According to one set of design rules, a minimum via opening for a contact is 1.2 microns and misalignment allowance must be 0.6 micron at either side of a gate. Therefore spacing between adjacent walls of adjacent gates must be 2.4 microns, as shown in FIG. 1.3b in order to allow for the 1.2 micron via with insulation remaining at the sidewalls of gates 12a and 12b in order to separate the substrate contact which will extend into openings 14a, 14b, and 14c from gates 12a and 12b.
It is beneficial to avoid having to allocate space for this misalignment.